As computer systems handle ever more complex operations, it is becoming increasingly more desirable to accelerate or augment the ability of computer systems to quickly handle interrupts from I/O devices and to use I/O subsystems which remove some of the burden of I/O interrupt processing from the central processing unit. These functions can be achieved with so called intelligent I/O ("I.sub.2 O") subsystems which may be used, for example, in PC servers.
The aim of the intelligent I/O subsystem is to improve the speed at which users access and manipulate text, graphic, video and audio data, maximizing the performance of the computer system. In addition intelligent I/O subsystems may free the host central processing unit from handling many interrupt driven I/O processing tasks and allow the host CPU to address secondary PCI bus devices through a PCI-to-PCI bridge. Intelligent I/O may be implemented by so-called add-on adapter cards or accelerator cards that are computer subsystems with embedded processors, memory, and peripheral components.
Since the demand for network computing is increasing, the nature of the I/O processing demand, is likewise increasing. In addition, the size of the data being accessed and its type is increasingly containing natural data elements such as video, audio, text and graphics.
One implementation of intelligent I/O is the Intel i960 RP processor. This processor includes a PCI-to-PCI bridge with an internal processor and memory control. Although the i960 RP processor has many advantages, some users may feel that the cost is excessive in view of the potential performance obtainable from the device. In addition, because it is a hierarchical type of system, it adds system complexity compared to a peer system. Generally, a peer system does not require additional system bridges such that additional devices are added in a subsidiary relationship to existing structure.
In addition, the Intel i960 part is normally implemented by permanently connecting that part to the system motherboard. Thus, this capability becomes an added expense borne by all computer purchasers regardless of whether they want I.sub.2 O capability.
Another approach to implementing intelligent I/O processing is disclosed in U.S. patent application, Ser. No. 08/658,634, filed Jun. 5, 1996 in the name of Whiteman, et al. entitled "Using Subordinate Bus Devices", which is hereby expressly incorporated by reference. This patent application discloses a system which allows an I.sub.2 O processing card to be added through a pair of cable connected bridges. The I.sub.2 O processor card may be inserted into an expansion bus and the system identifies the location of the card and the devices subsidiary thereto. A programmable device handles interrupt routing. The configuration cycle may be blocked for the subsidiary devices such that the central processing unit only recognizes the I.sub.2 O processing card rather than the subsidiary devices. Thus, communications between the processor and subsidiary devices must pass through the bridges to the I.sub.2 O processor card which, because of its internal computing capabilities, can enhance the performance of the subsidiary devices which have no such capabilities. Although this system has many advantages, it uses an essentially hierarchial system with additional bridges to implement the system and added cost, even for those users that prefer not to implement I.sub.2 O processing capabilities.
Still another approach to implementing I.sub.2 O processing involves a system with a primary host bridge and a secondary host bridge. An Intel i960 chip may be added to a slot in the primary host bridge and a slot in a connector connected to the secondary host bridge. The secondary host bridge may then be disabled so that all communications to or from the bus connected to the secondary bridge are re-routed through the primary host bridge. This system may introduce delays since it, in effect, deactivates an existing system bridge and requires communications originating from either of two buses to proceed through the single active bridge. Thus to some degree it may create the same kind of problems it aims to solve. Moreover, it necessarily requires all purchasers to bear a significant portion of the expense involved in achieving an I.sub.2 O capability that some users may not desire.
While the existing systems have many performance advantages and features, it would be highly desirable to provide a system for enabling the user to implement I.sub.2 O processing capabilities when and if desired but in a way which does not detract from the architecture of his or her existing computer system. In addition, it would be very advantageous to provide a way to make the system upgradeable to an I.sub.2 O system without imposing significant expense for the I.sub.2 O capability on all system purchasers.